I am using NI-1473R for image processing applications. Specifically, I use the 10-tap 8-bit Camera with DRAM example and build on it. My project requires me to do background subtraction. I am able to send an image from the HardDrive to the FPGA through FIFO. But I am not able to store the image in DRAM since it is already being used in the Vi. In this Vi, DRAM is used as a FIFO to hold intermediate image data from the camera between the packers (e.g. 80 to 256). There is no addressing as the CLIP interface just stores data on the banks of DRAM.
I am thinking of changing the DRAM from FIFO to Random Access to store my image, and perhaps hold the camera data in Bank0 and background image in the Bank1. How can I go about this? Will this cause a problem with write/read operations?
Also, Is there any example of DRAM storage NI-1473R? I was only able to find examples for PXI series FPGA.
many thanks,
Mehmet